- India has approved 10 semiconductor projects under the India Semiconductor Mission totaling ~₹1.6 lakh crore (US$18–19B) across six states, spanning fabs, OSAT/ATMP, and SiC/compound semiconductors.
- Tata Electronics anchors the push with a ₹91,000-crore Dholera fab (50,000 wafers/month, PSMC partner, 110–28nm) and a ₹27,000-crore Assam OSAT facility targeting ~48 million chips/day.
- Projects are underpinned by incentives offering up to 50% central fiscal support plus layered state benefits such as SGST exemptions, interest subsidies, and land/stamp duty relief.
- While aimed at automotive, telecom, power electronics and AI demand, major execution and supply-chain/talent risks remain and many first-chip timelines still point to mid-2026 to 2027.
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India’s semiconductor strategy has moved rapidly from policy launch (ISM scheme, ~₹76,000 crore outlay in 2021) toward execution and industrial mobilization. With 10 projects now approved, the country is strategically targeting gaps across the value chain: design, fabrication, package/test, and compound semiconductors (e.g. SiC). The clustering of projects in Gujarat (Dholera, Sanand) and Assam—and state policies offering fiscal layers—helps concentrate infrastructure, skills, and supply chain critical mass.
Tata Electronics emerges as the de facto anchor in India’s push. Its Dholera fab, in collaboration with PSMC, covers technology nodes from mature (110nm, 90nm) to more advanced (28nm) and is meant for applications spanning automotive, logic, display drivers and AI logic. Meanwhile, its Assam OSAT facility, with planned output of ~48 million units/day, fills a packaging/testing bottleneck. These two investments (₹91,000 crore + ₹27,000 crore) represent over half of ISM-approved project costs so far.
Regarding incentives: the central Modified Scheme for Semiconductor Fabs offers up to 50% of eligible project cost reimbursement on a pari-passu basis, making fabs viable in capital-intensive settings. States like Uttar Pradesh, Gujarat, Odisha etc. are enhancing state-level incentives (SGST exemptions for 5-10 years; employee expense reimbursements; interest subsidies). This stacking of incentives reduces the capital cost burden significantly.
However, challenges remain. The timeline for first chip output is still mid-2026 to 2027 in many fab projects, meaning supply chain readiness (equipment, chemicals, gases), talent (skilled fab engineers, clean-room operations), and securing anchor orders will test India’s execution capacity. Also, advanced node fabs (≤28nm) are yet to be proven domestically; similarly, SiC compound fabs are just entering approvals. Leadership in design/IP is nascent, and the global competitive environment (the US, Taiwan, Korea, China) for attracting foreign fab investment remains intense. Lastly, many incentives are front-loaded; long-term viability depends on market demand, export competitiveness, and regulatory consistency.
Strategic implications:
- India is shifting from import dependence to building indigenous capacity across OSAT/ATMP, mature fabs, and compound semiconductors—this aligns with global supply-chain reshoring trends.
- Countries and companies seeking resilient semiconductor supplies should view India as an emerging hub, especially for automotive, power electronics, display drivers, and logic nodes beyond 28nm.
- Investor risk is moderate-high: early entry advantage exists, but execution risks, global demand volatility, and technology obsolescence loom, especially for fabs at more advanced nodes.
Open questions include whether India can accelerate advanced node (<28nm) fabs; whether the supply of semiconductor equipment & materials (global licensing, supply chains) will meet domestic demand; how local IP/design firms will scale; and what policies will be sustained amid regulatory or political change.
Supporting Notes
- India has approved 10 semiconductor projects under ISM across six states with combined investments exceeding ₹1.6 lakh crore (~US$18-19 billion) as of late 2025.
- Tata Electronics’ Dholera fab investment is ₹91,000 crore, capacity ~50,000 wafers/month, nodes from 110nm to 28nm, partner PSMC.
- The Assam OSAT (Assembly & Test) facility: ₹27,000 crore investment, ~48 million chips/day output, targeting technologies including wire bond, flip chip, and ISP.
- Central Modified Scheme provides up to 50% fiscal support of eligible project cost for silicon CMOS fabs; state-level incentives include SGST exemptions of up to 10 years, employee expense reimbursement, interest subsidies etc.
- New approvals on August 12, 2025 include four projects in Odisha, Punjab, Andhra Pradesh (SiCSem, CDIL, ASIP etc.), with investment of ~₹4,594 crore, adding to the ISM-approved ecosystem.
- Projected timing: first outputs from many fabs expected in mid-2026 to 2027; Assam facility in high-volume production by second half 2025.
